Research Paper
Year: 2022 | Month: November | Volume: 9 | Issue: 11 | Pages: 91-95
DOI: https://doi.org/10.52403/ijrr.20221115
Design and Comparison of Full Adder Using TG Based 4:1 MUX
Mohammed Zeeshan A1, Dr. Kiran V2
1Master’s student, Department of Electronics and Communication Engineering, R.V College of Engineering, Affiliated to Visveswaraya Technological University, Bangalore, India
2Associate Professor, Department of Electronics and Communication Engineering, R.V College of Engineering, Affiliated to Visveswaraya Technological University, Bangalore, India
Corresponding Author: Mohammed Zeeshan A
ABSTRACT
The variousi analyses are based primarily on arithmetici circuit, notably with MUX designi, however this paper also investigates using a multiplexer to reduce power consumption. A 4:1 MUX is designed using CMOS transmission gatei logic (TGL), which hasi lower circuit complexity than traditional CMOS-based multiplexers. The NMOS and PMOS are coupled fori a strongi output leveli with a gaini in area, which is the centrali outcome of the proposed MUX. The designed circuit is dissipating 27.93 μW from a 1.8 V supply voltage in comparison to 43.85 μW of conventionali full adder.
Keywords: Mux, Full Adder, Transmission Gate, CMOS.
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