Research Paper
Year: 2022 | Month: November | Volume: 9 | Issue: 11 | Pages: 79-85
DOI: https://doi.org/10.52403/ijrr.20221113
Leakage Power Reduction in CMOS Logic Circuit Using Various Techniques
Priyanka1, Dr. Kiran V2
1Student, Department of ECE, RV College of Engineering, Bengaluru, India
2Associate Professor, Department of ECE, RV College of Engineering, Bengaluru, India
Corresponding Author: Priyanka
ABSTRACT
Low power nowadays High-power consumption has turned into a crucial design criterion for VLSI an emerging field. When it comes to energy efficiency, high power dissipation is not thought to be beneficial to battery life in the case of battery-powered applications. It reduces the efficiency, dependability, and cooling expenses of battery life. The high-frequency dynamic variation of inputs is heavily influenced by switching and short-circuit leakage power. There are several common methods for reducing the power consumption of circuits. The average power consumption consists of static and dynamic power consumption. The power consumption comparison of LECT0R, LCNT, Stack 0N0FIC, and SAP0N of various low-power techniques. These circuits are simulated in the cadence tool.
Keywords: LECT0R, LCNT, Stack 0N0FIC, and SAP0N Techniques, cadence tool (90nm).
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